✨ About me
I am a student in the CSSLAB (Computer System Security Lab) at UNIST (Ulsan National Institute of Science and Technology, South Korea), under
supervision of Prof. Hyungon Moon.
My research interests are in system security, hardware security, program analysis, and secure hardware system.
I love swimming, programming and watching Netflix. If you have any questions, feel free to contact me.
📄 Research Interests
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Building secure software system.
Improving the security of operating systems. Preventing exploitation of kernel bugs, finding new kernel bugs.
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Finding software bugs
Static analysis, Symbolic execution, and Fuzzing.
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Secure Hardware Extension
Hardware extensions for secure system.
Improving the security of operating systems. Preventing exploitation of kernel bugs, finding new kernel bugs.
Static analysis, Symbolic execution, and Fuzzing.
Hardware extensions for secure system.
🔐 Research Goal
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Ulsan National Institute of Science and Technology
Master of Science in Computer Science
Ulsan, KoreaMar. 2019 - Feb. 2021
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University of Science and Technology
Master of Information Security Engineering
Daejeon, KoreaMar. 2018 - Aug. 2018
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Dalian Ocean University
Exchange Student
Dalian, ChinaAug. 2016 - Feb. 2017
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Pukyong National University
Bachelor of Engineering in information and communication engineering
Busan, KoreaMar. 2013 - Feb. 2018
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ETRI(Electronics and Telecommunications Research Institute)
Software Engineer
- Indoor Localization: We researched to improve the accuracy of beacon recognition indoors.
Daejeon, KoreaJul. 2017 - Oct. 2017
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Physical Address-based Kernel Code Integrity Protection with a Small Hardware Extension for Embedded Systems [PRIVLOCK]
This project presents that a small architectural extension enables a physical address-based mechanism to stop this threat on an embedded system without relying on the page table integrity. PRIVLOCK lets, at boot time, the kernel define the physical address ranges containing its code. At run time, PRIVLOCK ensures that the content within the range is not manipulated and that only the instructions from those pages are executed while the processor is running in supervisor mode. We implemented PRIVLOCK by extending the Rocket Chip Generator and used the Freedom U500 V707 FPGA dev kit to evaluate the system on an FPGA. The experimental results show that PRIVLOCK incurs low performance overhead < 0.5%, with a slight increase in area 0.13% and power 0.9%.
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Extracting ISA semantic from a processor RTL [SemTracter] - Master’s Thesis
This work presents SemTracter that extracts the instruction semantics automatically from a processor implemented in hardware-description language (HDL), at register-transfer level (RTL). SemTracter obtains each instrucion semantics by simulating the processor RTL symbolically and compile the result to formal instruction semantics using the Sail language. Our evaluation of SemTracter using a small RISC-V processor RTL shows that SemTracter can extract semantics of basic instructions from a 5-stage processor implemented in RTL. SemTracter extracted most of the RISC-V 32-bit integer base user-level ISA (RV32I) instructions that the RTL implements, and it took 9 hours to extract the semantics. The generated semantics matches the manually written one.
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➔ Safe load kernel loadable module(LKM)
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🏆 Awards
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KISBIC - Korea information security BOB Idea cup
KETRI(Korea Information Technology Research Institute), Korea
Create excellent information protection ideas and raise public awareness of security.
Netizen special prizeFeb. 2015
🎶 Activities
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CERT-IS
Pukyong National University Security Club
Mar. 2014 - Feb. 2018
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Microsoft Student Partners 8th
Microsoft Korea
Aug. 2014 - Aug. 2015
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I want to make secure computer systems for everyone.